Simulation of IEEE 754 Standard Double Precision Multiplierusing Booth Techniques

摘要

Multiplication is an important fundamental function in arithmetic operations. It can be performed with the help of different multipliers using different techniques. The objective of good multiplier is to provide a physically compact high speed and low power consumption. To save significant power consumption of multiplier design, it is a good direction to reduce number of operations thereby reducing a dynamic power which is a major part of total power dissipation. The main objective of this Dissertation is to design "Simulation of IEEE 754 standard double precision multiplier" using VHDL