A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model

摘要

Our aim is the development of a novel probabilistic method to estimate the powerconsumption of a combinational circuit under real gate delay model handling temporal,structural and input pattern dependencies. The chosen gate delay model allows handlingboth the functional and spurious transitions. It is proved that the switching activityevaluation problem assuming real gate delay model is reduced to the zero delay switchingactivity evaluation problem at specific time instances. A modified Boolean function,which describes the logic behavior of a signal at any time instance, including timeparameter is introduced. Moreover, a mathematical model based on Markov stochasticprocesses, which describes the temporal and spatial correlation in terms of the associatedzero delay based parameters is presented. Based on the mathematical model andconsidering the modified Boolean function, a new algorithm to evaluate the switchingactivity at specific time instances using Ordering Binary Decision Diagrams (OBBDs) isalso presented. Comparative study of benchmark circuits demonstrates the accuracy andefficiency of the proposed method.