Placement and Routing for Performance-Oriented FPGA Layout

摘要

This paper presents a performance-oriented placement and routing tool for field-programmablegate arrays. Using recursive geometric partitioning for simultaneousplacement and global routing, and a graph-based strategy for detailed routing, our tooloptimizes source-sink pathlengths, channel width and total wirelength. Our resultscompare favorably with other FPGA layout tools, as measured by the maximumchannel width required to place and route several benchmarks.