SysML-Based Integration of System Design and Failure Models and Safety Verification by Simulation

摘要

The present study aims to develop an improved SysML-based integration model that can be used to perform system design and failure analysis simultaneously and verify safety activities. In recent studies, the safety of a system has been evaluated by modeling the system design and failure analysis. However, because the models developed in there were created using different modeling languages, it was not easy to carry out system design and safety activities efficiently. Furthermore, studies using UML or SysML-based failure models for deriving safety requirements have shown that these models have limited applicability to safety analysis and verification. To solve this problem, we propose to explore an advanced method for failure modeling and verification. First, an improved SysML-based integration model was developed, which can combine system design and safety verification activities interactively. Next, we transformed the integration model for analysis into a simulation model for verification with the safety measures derived from the failure model. A case study of the safety design for an automotive system was then followed with the analysis model and simulation results to verify the safety of the automotive system. Through the case study, the concept of safety design and verification became more explicit and the proposed method proved to be useful.