Through technology development, VLSI fabrication is becoming smaller in size which causes muchsensitivity of VLSI circuit to noise effects especially soft error. In this paper, we present a method tomitigate soft error in combinational logic gates based on 65 nm technology that is able to reduce thepossibility of noise propagation in combinational logic gate. We evaluate our result based on ISCAS 85benchmark circuit. Through DFS algorithm and using analytical model derived by stimulation of eachcombinational logic gate in transistor layer, soft error is processed in paths of ISCAS 85 circuit benchmarkand a single buffer logic gate is added to the end of the paths that have more potential to be affected by softerror. Therefore, possibility of soft error distribution through circuit benchmark is measured. The buffergates that mitigate soft errors on the benchmark paths are kept and others are eliminated. After processing,new circuit benchmark is available that includes added buffer logic gate to only critical paths. This is morereliable than initial ISCAS85 circuit benchmark in terms of illuminating soft error. The results show thatpossibility of soft error distribution is reduced intelligently and due to adding buffer gate to just suspiciouspaths of benchmark, power and delay are optimum.
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