Analysis Of DPA Resistant Adiabatic Logic Style In Low Power Adder Circuits

摘要

This paper analyzes the ability of adiabatic logic with charge sharing mechanism to implement low power adder circuits. Power consumption comparison with variety of adiabatic logic structures and static CMOS logic is made. Simulation results show that charge sharing adiabatic technique achieves 81% power reduction on the average with reference to 2N-2N2P, ECRL and SyAL logic. Hence charge sharing DPA resistant logic style is evaluated through implementation of adder circuits which are used as secondary elements in cryptographic algorithms.