The Design of High Speed FIR Filter using Improved DA Algorithm and it’s FPGA Implementation

摘要

when the DA (distributed arithmetic) algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is difficult to achieve the best configuration in the coefficient of FIR filter, the storage resource and the computing speed. According to this problem, the paper provides the detailed analysis a nd discussion in the algorithm, the memory size and the look up table speed. Also, the corresponding optimization and improvement measures are discussed and the concrete Hardware realization of the circuit is presented. The design based on Altera EP2C5T144 C8 chips is synthesized under the integrated environment of QUARTUS II 7.1. The results of Simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough comp ared to the traditional FPGA realization.