DESIGN AND IMPLEMENTATION OF CMOS ANALOG-TO-DIGITAL CONVERTER USING VOLTAGE-TOTIME AND DELAY LINE BASED TIMETO- DIGITAL CONVERTION

摘要

With the advancements in the VLSI CMOS fabrication technology, the Software Defined Radio (SDR) receivers and digital circuits require high accuracy, high speed and low power Analog-to-Digital Converters (ADCs). These requirements cannot be satisfied by the currently available conventional Analog-to-Digital Converters. The Time based Analog-to-Digital Converter (T-ADC) promises to provide high speed and low power dissipation than conventional ADCs. The Time based Analog-to-Digital Converters consists of two important blocks such as Voltage-to-Time Converter (VTC) and Time-to-Digital Converter (TDC). Here a time-domain folding ADC with high area efficiency and high resolution is designed. The converter front end had a non-interleaving Voltage-to-Time Converter (VTC) and back-end of time interleaved delay cell based Time-to-Digital Converter (TDC) with differentially sense amplifier based flip-flops that achieves high conversion speed and low power consumption. This work was implemented in 130nm CMOS technology. The overall delay of the total Analog-to-Digital Converter is 21.791nanoseconds and power dissipation of 424.5microwatts.