Exploration of power delay product [PDP] on feedback based dual edge triggered flip flop utilizing dual sleep and dual slack approach

摘要

In Modern Digital electronics, the low power circuits become the essential part. As the flip-flops are basic storage components utilized as a part of significant number of digital circuits, so they must be planned with upgraded power consumption. Power dissipation is the important factor in Dual Edge Triggered flip flop. Low glitch and low power DET flip-flops are based on a feedback element utilizing dual sleep and dual slack approach are proposed to keep up a steady throughput while working at half clock frequency. Feedback elements are utilized to reduce the switching activities because of input signal transitions. In the proposed design the internal nodes will not respond to input signal variations. As the innovation is scaling from micron technology to profound submicron technology the leakage power is one of the parameter which impacts the circuit execution, by utilizing these dual sleep and dual slack techniques are proposed and compared to existing DET flip-flop designs utilizing 45nm CMOS technology. The simulation result demonstrates that Conditional Toggle flip-flop using dual sleep and dual slack techniques shows better Power Delay Product (PDP).