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Utilization of Power Gating Technique for the Analysis of MPSoC Based On Dual Feedback Edge Triggered Flip Flop

机译：基于双反馈边缘触发触发器的MPSOC分析功率门控技术的利用

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Satyaraj D; Bhanumathi V;
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年度 2021
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1. Exploration of power delay product [PDP] on feedback based dual edge triggered flip flop utilizing dual sleep and dual slack approach [J] . S. Karunakaran, Boddupally Harshitha, B. Poonguzharselvi, International Journal of Engineering & Technology . 2018,第4期

机译：利用双睡眠和双松弛方法的基于反馈的双沿触发触发器的功率延迟乘积[PDP]的探索
2. Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique [J] . Sabu Neethu Anna, Batri K. Journal of circuits, systems and computers . 2020,第8期

机译：基于功率高效的TG双边缘触发触发器的设计与分析堆叠技术
3. Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique [J] . Shen Jizhong, Geng Liang, Wu Xuexiang Journal of circuits, systems and computers . 2015,第7期

机译：基于时钟触发边沿控制技术的低功耗脉冲触发触发器
4. A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique [C] . Kavali Krishna, Rajendar S., Bhargava P. Vamshi International Conference on Electrical, Electronics, Signals, Communication and Optimization . 2015

机译：基于时钟门控脉冲抑制技术的新型低功耗双沿触发触发器
5. Dual-Edge Triggered Pulsed Flip-Flop With High Performance And High Soft-Error Tolerance. [D] . Gong, Jianping. 2011

机译：具有高性能和高软误差容限的双沿触发脉冲触发器。
6. Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II [O] . Farshid Keivanian, Nasser Mehrshad, Abolfazl Bijari -1

机译：拟议的双边沿触发静态D型触发器中的MOSFET沟道宽度和电源电压的多目标优化采用模糊非支配排序遗传算法II
7. Design of Low Power Dual Edge Triggered Flip Flop Based On Signal Feed through Scheme [O] . S.SUJA THA, M.VIGN ESH 2014

机译：基于信号馈线的低功耗双边缘触发触发器的设计
8. Improvement of Production Techniques to Increase the Reliability of Silicon Planar Epitaxial: Transistor (WX4001) Logic Gate (Wm 201) Flip-Flop (Wm 202) AC Binary (Wm 213) [R] . Hamill, A. T. 1964

机译：改进生产技术以提高硅平面外延的可靠性：晶体管（WX4001）逻辑门（Wm 201）触发器（Wm 202）aC二进制（Wm 213）

Utilization of Power Gating Technique for the Analysis of MPSoC Based On Dual Feedback Edge Triggered Flip Flop

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