Review and Analysis of the Impacts and Effects on Low Power VLSI Circuits Operating in Subthreshold Regime

摘要

In ultra low power portable devices set towards realizing a long battery life, low energy consumption per operation is the primary design constraint. Hence, operating the circuits in weak inversion or the sub-threshold region, with the subthreshold leakage current acting as the primary computing current, turn out to be a promising solution. Though such a methodology limits the performance in terms of speed, it exhibits a lot of benefits in terms of reduced dynamic power and leakage power, added with high transconductance gain. In the subthreshold regime, the high sensitivity of the devices to the process, voltage and temperature (PVT) variations prove to be a major challenge to be tackled, due to the exponential dependence of drain current on the threshold voltage VT. In this paper, the operational behaviours of VLSI circuits, while operating in the weak inversion region are illustrated with explicit simulation results, waveforms and discussions. Moreover, the lack of robustness of the device in the subthreshold regime is also analyzed. The elimination of the PVT variability issues by employing body biasing strategies is explored. Each of these analyses use precisely exemplified simulation methodologies. The results and discussions are depicted through ample simulation results. The impact of technology scaling on VLSI circuits in the subthreshold regime is explored. Minimum energy point, optimum Vdd and optimum VT are also evaluated. It is followed by the channel upsizing, which is considered to be the most potential circuit level technique for addressing most of the issues in the subthreshold regime. The entire analyses and study are done with the use of a 16-bit CLA adder as the benchmark circuit. PTM (Predictive Technology Models) models of 32nm, 45nm, 65nm, 90nm, 130nm and 180nm have been used in the simulations using the industry standard EDA tool.