Implementation Of Low Power And Low Energy Synchronous Sapt Logic

摘要

This paper presents the design and implementation of a low-energy synchronous self timed logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize for very low power computation by leakage current controlling networks with reduced supply voltages. The introduction of synchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. A simple XOR gate is implemented in SAPTL architecture. The power consumption of the SAPTL is less