A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

摘要

References(17) A clock and data recovery (CDR) circuit for 1.5–5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10?12.