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Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

机译:沟道厚度对栅嵌入式纳米SOI MOSFET的电特性和串联电阻影响的建模

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Ultrathin body (UTB) and nanoscale body (NSB) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.
机译:超薄体(UTB)和纳米体(NSB)SOI-MOSFET器件具有相似的W / L,但其沟道厚度分别为46 nm和低于5 nm,是通过选择性的“栅凹”工艺制造的。相同的硅晶片。发现它们在室温下测量的电流-电压特性出人意料地相差几个数量级。我们通过考虑严重的迁移率降低和巨大的串联电阻的影响来分析此结果,发现最后一个看起来更连贯。然后,可以通过对取决于栅极电压的漏极源极串联电阻进行积分来分析得出NSB的电特性。本文首次报道了沟道厚度对串联电阻的影响。该影响被集成到分析模型中,以描述饱和电流随沟道厚度的变化趋势。这种建模方法可能有助于解释其他纳米器件的异常电学行为,在这些纳米器件中,串联电阻和/或迁移率的下降非常令人担忧。

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