SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designedand successfully mapped into a FPGA chip in our ECE department. In this paper, we useSMaRT to run the well-known encryption algorithm, Data Encryption Standard. Forinformation security purposes, encryption is a must in today’s sophisticated and ever-increasingcomputer communications such as ATM machines and SIM cards. For comparison andevaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-typeoff-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only14% longer in terms of the static number of instructions but about 10 times faster in terms of thenumber of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5-address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructionsresulting in significant improvement in static number of instructions hence code size as well asperformance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept oflocality of reference in using the MSBs of the registers in non-subroutine branch instructionsstays valid with a remarkable hit rate of 95%.
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