机译:基于残差量化的28nm CMOS自适应分辨率准电平交叉采样ADC
School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland;
School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland;
Department of Measurement and Electronics, AGH University of Science and Technology, Kraków, Poland;
School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland;
Capacitors; Signal resolution; Timing; Logic gates; Quantization (signal); Clocks; Solid state circuits;
机译:基于28-NM CMOS中的残留量化的自适应分辨率准分流adc
机译:9.1-ENOB 6mW 10位500-MS / s流水线SAR ADC,具有在28nm CMOS中进行电流模式残留处理的功能
机译:一个91.0-DB SFDR单粗双精度流水线 - SAR ADC,28-NM CMOS中的基于分割的背景校准
机译:在28nm FD-SOI CMOS中具有增强的线性度的基于批量输入VCO的Sigma-Delta ADC
机译:采用65nm CMOS技术的基于时间的低功耗,低失调5位1 Gs / S闪存ADC设计
机译:具有嵌入式PMOSFET的鲁棒和锁定的免疫LVTSCR器件用于28 nm CMOS过程中的ESD保护
机译:基于Dickson-Charge-Pump的基于时间的ADC在28-NM CMOS中的电压与时间转换