Designing in power-down test circuits

摘要

Built-in self-test circuitry that is active only during testing is described. The benefit of these types of circuits is that defects that are not uncovered within the test circuitry will not contribute to failures in the host's ICs. Thus, the overall reliability of the IC in its targeted application should increase. Also, since the test circuitry is inactive, there will be less overall power consumption. Layout issues, simulation models, and interface/isolation considerations are discussed. Some general design guidelines are given.