EASILY TESTED INTEGRATED CIRCUIT, DESIGNING METHOD FOR EASILY TESTING INTEGRATED CIRCUIT, AND STORAGE MEDIUM FOR READING PROGRAM FOR DESIGNING FOR EASILY TESTING INTEGRATED CIRCUIT BY COMPUTER

摘要

PROBLEM TO BE SOLVED: To achieve a high failure detection efficiency and at the same time achieve testing at an actual operation speed while suppressing the increase in a test series length regarding an integrated circuit including such order circuit as a controller. ;SOLUTION: An invalid state generation logic circuit 20 is added to generate an invalid state that cannot be reached from a reset state by a normal state transition out of states included in each test pattern being obtained by performing a test generation to a combination circuit excluding a state register 12 by assuming that the state of the state register 12 can be observed and can be arbitrarily set. Also, a multiplexer 22 for selecting whether either the output of a next state generation logic circuit 10 or that of an invalid state generation logic circuit 20 is inputted to the state register 12 by a state transition mode selection signal (t) is added, and at the same time the output of the multiplexer is outputted externally as a state output signal t_- out to observe a signal that is equivalent to pseudo external output when the above test generation is made.;COPYRIGHT: (C)1999,JPO