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Scalable Processor Instruction Set Extension

机译:可扩展处理器指令集扩展

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The limitations of conventional processor architectures are becoming increasingly evident. The growing importance of stream-based applications makes coarse-grained, dynamically reconfigurable architectures an attractive alternative. They combine the performance of ASICs, which are risky (in terms of flexibility and usability, because of fixed functional sets) and expensive (in development and mask costs), with the flexibility of traditional processors. In spite of today's VLSI possibilities, basic microprocessor architecture concepts are still the same as 20 years ago. Conventional microprocessors' main processing unit, the data path, follows the same style guidelines as its predecessors. Although the development of pipelined architectures or superscalar concepts in combination with data and instruction caches increases a modem microprocessor's performance and allows higher frequency rates, the main concept of a static data path remains. Therefore, each instruction is a composition of the processor's basic operations.
机译:常规处理器体系结构的局限性越来越明显。基于流的应用程序的重要性日益增长,使得具有粗粒度,可动态重新配置的体系结构成为有吸引力的替代方案。它们将ASIC的性能与传统处理器的灵活性相结合,而ASIC的性能具有风险(在灵活性和可用性方面,由于固定的功能集),并且价格昂贵(在开发和掩膜成本方面)。尽管存在当今的VLSI,但基本的微处理器体系结构概念仍与20年前相同。常规微处理器的主要处理单元,即数据路径,遵循与其前任相同的样式准则。尽管流水线架构或超标量概念与数据和指令高速缓存相结合的发展提高了调制解调器微处理器的性能并允许更高的频率速率,但静态数据路径的主要概念仍然存在。因此,每条指令都是处理器基本操作的组成部分。

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