An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories

摘要

THE TECHNOLOGICAL EVOLUTION of the IC fabrication process, consisting of device shrinking, power supply reduction, and increasing operating speeds, has significantly reduced the manufacturing yield and reliability of very deep-submicron (VDSM) ICs when various noise sources are present, as recent roadmaps (the International Technology Roadmap for Semiconductors, Medea, and IEEE Design & Test) have demonstrated. As a result, more and more applications must be robust in the presence of multiple faults. Consequently, fault tolerance in storage devices such as high-density and highspeed memories operating at low voltage, is a main concern nowadays and thus the focus of this work.