机译:具有内置缓存的低功耗,低延迟DRAM的控制器架构
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;
Random access memory; DRAM; Microprocessors; Delays; Transistors;
机译:合并的DRAM /逻辑LSI的高性能/低功耗高速缓存架构
机译:缓存DRAM架构:具有片上缓存的DRAM
机译:一系列DRAM缓存的控制器的正式建模和验证
机译:ReTagger:用于DRAM缓存架构的高效控制器
机译:低延迟和低功耗的NOC架构
机译:用于低延迟和低功耗3D堆叠DRAM的DRAM中缓存管理
机译:DCa:DRam-Cache-aware DRam控制器