Tri-level resist processing for GMR heads

摘要

Tri-level resist-processing techniques, considered for microelectronic device fabrication for more than 20 years, apply very well to situations where the ability to resolve fine photolithographic images is compromised by thickness variations in the imaging photoresist due to variations in the underlying topography. This usefulness explains why the trends in semiconductor manufacturing toward planarization of multilevel metal interconnect layers and global planarization at the device isolation layer (shallow trench isolation) have kept implementation of tri-level resist processes from becoming commonplace for ICs.