A 3 V 6-bit 70 MSPS dual CMOS A/D converter for DBS (direct broadcasting for satellite)

摘要

In a front-end receiver of DBS (direct broadcasting for satellite), the A/D converter, which converts I/Q signals of the QPSK demodulator into the digital domain, has an important role in determining the system performance. A 3 V dual A/D converter which has a 6-b resolution and a 70 MSPS conversion rate is proposed. It has a dual flash architecture in which comparators use an auto-zero offset cancellation technique with 0.65 /spl mu/m double-poly and double-metal CMOS technology, the experimental prototype of the proposed A/D converter has /spl plusmn/0.7 LSB INL (integral non-linearity error) and /spl plusmn/0.9 LSB DNL (differential non-linearity error).