Architecture and VLSI implementation of digital symbol timing recovery for DTV receivers

摘要

Completely digital symbol timing recovery architectures have advantages over the conventional mixed analog and digital approach, such as ease of system integration (especially for VLSI implementations) and flexible sampling rates. This paper is split into two main parts. The first part describes a digital symbol timing recovery architecture designed for digital television (DTV) receivers and also presents the associated design tradeoffs. The second part discusses an important aspect of the VLSI implementation of the architecture, which is the design and verification of the system clocking scheme.