Incorporating selective victim cache into GPGPU for high-performance computing

摘要

Contemporary general-purpose graphic processing units (GPGPUs) successfully parallelize anrnapplication into thousands of concurrent threads with remarkably improved performance. Suchrnmassive threads will compete for the small-sized first-level data (L1D) cache, leading to an exaggeratedrncache-thrashing problem, whichmay degrade the overall performance significantly. In thisrnpaper, we propose a selective victim cache design to enable better data locality and higher performance.rnInstead of a small fully associative structure,we first redesign the victim cache as a setrnassociative structure that is equivalent to the original L1D cache to suit the GPGPU applicationsrnwith massive concurrent threads. To keep themostly used data in L1D for better operand service,rnwe apply a simple prediction scheme to avoid costly block interchanges and evictions. To furtherrnsave the area for data storage, we propose to leverage the unallocated registers and sharedrnmemory entries to hold the victim cache data. The experiments demonstrate that our proposedrnapproach can increase the on-chip data cache hit rate considerably and deliver a better performancernwith negligible changes to the baseline GPGPU architecture. For example, our selectivernvictim cache design can improve the performance by 41.3% on average, achieving 54.7% increasernin data cache hit rate and 21.8% reduction in block interchanges and evictions.