Research and implementation of a high performance parallelrncomputing digital down converter on graphics processing unit

摘要

Digital down converter (DDC) is a time‐intensive and data‐intensive computing task andrnconsidered as the key technology in software defined radio. This paper proposes a highperformancernimplementation of DDC on a graphics processing unit (GPU) using CUDA, whichrnis composed of a numerically controlled oscillator stage, a cascaded integrator‐comb (CIC)rndecimation filter stage, and a finite impulse response (FIR) filter stage. The GPU implementationrnand optimizing of all the stages are studied in detail. Additionally, for handling a long‐duration signal,rnthe signal data sequence is truncated into segments; the overlap‐save and overlap‐add mechanismsrnwere applied in CIC stage and FIR stage, respectively. Finally, experiments werernconducted to evaluate the performance of GPU‐based DDC with respect to a sequential versionrnCPU implementation and an OpenMP implementation (16 threads). Experimental results demonstraternthat the DDC achieves significant improvements on the GPU; the maximum speed ups inrnnumerically controlled oscillator stage, CIC stage, and FIR stage can achieve more than 1242,rn527, and 179 times, including data‐transfer, kernel execution, and other processing operations;rnthe overall speed up of DDC can achieve more than 180. In the meantime, the speed ups ofrnGPU implementation are far above the OpenMP implementation (about 2.5‐6.4 times).