An O(n)-depth polynomial-size combinational circuit algorithm is proposed for n-bit modular exponentiation, i.e., for the computation of x/sup v/ mod m for arbitrary integers x, y, and m represented as n-bit binary integers, within bounds 2/sup n-1//spl les/m>2/sup n/ and 0/spl les/Ix, y>m. The algorithm is a generalization of the square-and-multiply method. The terms (x(2/sup l/)mod m)s for all is /spl epsiv/{0, n-1} are computed in ~n-1/~/spl alpha/logn parallel rounds, each of which computes ~/spl alpha/logn consecutive terms, where /spl alpha//spl ges/1/logn. The circuit implementing a round has depth O((1+/spl alpha/)logn) and size O(n/sup 2(1+/spl alpha/)/) yielding a circuit for modular exponentiation of depth O(1+/spl alpha///spl alpha) and size O(n/sup 3+2/spl alpha////spl alpha/logn).
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