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State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores

机译:具有多线程有序内核的多核处理器中寄存器文件的状态保持电源门控

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In this work, we investigate state-retentive power gating of register files for leakage reduction in multicore processors supporting multithreading. In an in-order core, when a thread gets blocked due to a memory stall, the corresponding register file can be placed in a low leakage state through power gating for leakage reduction. When the memory stall gets resolved, the register file is activated for being accessed again. Since the contents of the register file are not lost and restored on wakeup, this is referred to as state-retentive power gating of register files. While state-retentive power gating in single cores has been studied in the literature, it is being investigated for multicore architectures for the first time in this work. We propose specific techniques to implement state-retentive power gating for three different multicore processor configurations based on the multithreading model: 1) coarse-grained multithreading, 2) fine-grained multithreading, and 3) simultaneous multithreading. The proposed techniques can be implemented as design extensions within the control units of the in-order cores. Each technique uses two different modes of leakage states: low-leakage savings and low wake-up and high-leakage savings and high wake-up latency. The overhead due to wake-up latency is completely avoided in two techniques while it is hidden for most part in the third approach, either by overlapping the wake-up process with the thread context switching latency or by executing instructions from other threads ready for execution. The proposed techniques were evaluated through simulations with multiprogrammed workloads comprised of SPEC 2000 integer benchmarks. Experimental results show that in an 8-core processor executing 64 threads, the average leakage savings were 42 percent in coarse-grained multithreading, while they were between seven percent and eight percent for finegrained and simultaneous multithreading.
机译:在这项工作中,我们研究了寄存器文件的状态保持电源门控,以减少支持多线程的多核处理器中的泄漏。在有序内核中,当线程由于内存停滞而被阻塞时,可以通过电源门控将相应的寄存器堆置于低泄漏状态,以减少泄漏。解决内存停顿后,将激活寄存器文件以再次访问。由于寄存器文件的内容不会在唤醒时丢失和恢复,因此称为寄存器文件的状态保持电源门控。尽管在文献中已经研究了单核中的状态保持功率门控,但这项工作首次在多核架构中得到了研究。我们基于多线程模型提出了用于针对三种不同的多核处理器配置实现状态保持功率门控的特定技术:1)粗粒度多线程,2)细粒度多线程和3)同步多线程。所提出的技术可以被实现为有序堆芯的控制单元内的设计扩展。每种技术都使用两种不同的泄漏状态模式:低泄漏节省和低唤醒以及高泄漏节省和高唤醒延迟。两种方法完全避免了由于唤醒等待时间引起的开销,而在第三种方法中大部分都将其隐藏了,要么通过将唤醒过程与线程上下文切换等待时间重叠,要么通过执行其他准备执行的线程来执行。通过对包含SPEC 2000整数基准的多程序工作负载进行仿真,对提出的技术进行了评估。实验结果表明,在执行64个线程的8核处理器中,粗粒度多线程的平均泄漏节省为42%,而细粒度和同时多线程的平均泄漏节省为7%至8%。

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