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NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging

机译:基于NoC的FPGA加速用于Monte Carlo仿真及其在SPECT成像中的应用

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As the number of transistors that are integrated onto a silicon die continues to increase, the compute power is becoming a commodity. This has enabled a whole host of new applications that rely on high-throughput computations. Recently, the need for faster and cost-effective applications in form-factor constrained environments has driven an interest in on-chip acceleration of algorithms based on Monte Carlo simulations. Though Field Programmable Gate Arrays (FPGAs), with hundreds of on-chip arithmetic units, show significant promise for accelerating these embarrassingly parallel simulations, a challenge exists in sharing access to simulation data among many concurrent experiments. This paper presents a compute architecture for accelerating Monte Carlo simulations based on the Network-on-Chip (NOC) paradigm for on-chip communication. We demonstrate through the complete implementation of a Monte Carlo-based image reconstruction algorithm for Single-Photon Emission Computed Tomography (SPECT) imaging that this complex problem can be accelerated by two orders of magnitude on even a modestly sized FPGA over a 2 GHz Intel Core 2 Duo Processor. The architecture and the methodology that we present in this paper is modular and hence it is scalable to problem instances of different sizes, with application to other domains that rely on Monte Carlo simulations.
机译:随着集成到硅芯片上的晶体管数量的不断增加,计算能力正成为一种商品。这使得大量依赖高吞吐量计算的新应用程序成为可能。近来,在形状因数受限的环境中对更快且具有成本效益的应用的需求已引起对基于蒙特卡洛模拟的算法的片上加速的兴趣。尽管具有数百个片上算术单元的现场可编程门阵列(FPGA)对于加速这些令人尴尬的并行仿真显示出巨大希望,但在许多并行实验之间共享对仿真数据的访问方面仍然存在挑战。本文提出了一种基于芯片上网络通信的片上网络(NOC)范式来加速Monte Carlo仿真的计算架构。我们通过针对单光子发射计算机断层扫描(SPECT)成像的基于Monte Carlo的图像重建算法的完整实现,证明了即使在2 GHz Intel Core上中等大小的FPGA上,这个复杂的问题也可以加速两个数量级。 2 Duo处理器。我们在本文中介绍的体系结构和方法论是模块化的,因此可以扩展到不同大小的问题实例,并应用于依赖于蒙特卡洛模拟的其他领域。

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