Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units

摘要

Three-dimensional stacked integrated circuits (3D-SICs) have been expected to overcome the limitations of conventional two-dimensional (2-D) implemented circuits. Since a stacking strategy affects the performance and the power consumption of 3D-SICs, this paper examines two stacking strategies for designing the 3-D stacked floating-point fused multiply-add (FP-FMA) module which contains four FP-FMA units. Experimental results show that a coarse-grain stacking strategy is suitable for reducing critical path delay of the 3-D stacked FP-FMA module. On the other hand, a fine-grain stacking strategy is suitable for reducing power consumption. The 3-D stacked FP-FMA module which is designed based on a fine-grain stacking strategy achieves an 8.4% critical path delay reduction and an 18% average power reduction compared with the 2-D implementation.