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机译:基于WLP-FDTD的封装与PCB电源/地平面之间噪声耦合的时域分析
Key Laboratory of Ministry of Education of China for Research of Design and Electromagnetic Compatibility of High Speed Electronic Systems, Shanghai Jiao Tong University, Shanghai, China;
Key Laboratory of Ministry of Education of China for Research of Design and Electromagnetic Compatibility of High Speed Electronic Systems, Shanghai Jiao Tong University, Shanghai, China;
Key Laboratory of Ministry of Education of China for Research of Design and Electromagnetic Compatibility of High Speed Electronic Systems, Shanghai Jiao Tong University, Shanghai, China;
Time-domain analysis; Integrated circuit modeling; Finite difference methods; Couplings; Equivalent circuits; Integrated circuit interconnections; Numerical stability;
机译:通过多层封装和PCB中的切口分析和抑制电源/接地平面腔之间的SSN噪声耦合
机译:利用高效的二维FDTD /集总元件方法对封装与PCB电源/接地平面之间的噪声耦合进行建模
机译:使用挠性接地结构的紧凑型宽带电磁带隙结构,用于多层封装和PCB中的电源/接地噪声抑制
机译:考虑电源和接地层的高密度多层封装和PCB的高效同时开关噪声分析
机译:多层电源/地平面中噪声耦合的建模和分析。
机译:基于平面内耦合和平面外耦合的旋光等离子体表面
机译:通过多层封装和pCB中的切口分析和抑制电源/接地平面腔之间的ssN噪声耦合