Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits

摘要

Leakage power dissipation is a serious concern in deep nanometer devices. Low power design methodology is often adopted in VLSI circuits and systems to minimize power; however, this is achieved at the cost of performance penalty. In this paper, we first review the existing circuit techniques for leakage minimization. A new circuit technique is then proposed which is designed intelligently by mixing a pair of dynamic threshold sleep transistors and a pair of helper transistors. The performance of the proposed technique is investigated in terms of area, power, delay and power-delay product. Extensive SPICE simulation with 32 nm process technology shows a significant reduction in power, delay and power-delay product.