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Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm Ⅱ

机译:基于优化的栅极扩散输入法使用非主导分类遗传算法的基于栅极扩散输入法的可逆幅度算术单元Ⅱ

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摘要

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by theMonte Carloprocedure in standard 32 nm technology utilizing theSynopsysHSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers.
机译:使用简单单元的栅极扩散输入(GDI)方法使得可以设计具有减少的芯片面积和更短的复杂性的低功率逻辑门。在这项工作中,使用适当的标准可逆栅极(CNT)场效应晶体管(CNTFET)的适当标准可逆栅极基于单位优化可逆逻辑幅度算术单元(RMAU)电路的新颖设计。基于修改GDI(M介绍了纳米粒子的方法。为了优化所提出的电路的性能,并且为了实现最小功耗和传播延迟,使用Matlab工具中的非主导排序遗传算法II(NSGA-II)来调整晶体管尺寸。仿真结果表明,与使用类似的设计方法但对应结构的非优化的RMAU电路相比,在所提出的优化算术单元的最坏情况下延迟和功耗中评估优异延迟和功耗的改进。利用ThesynopsyopsyShspice Simulator的标准32 nm技术,在标准32nm技术中,不同的工艺参数(例如CNTs的直径)和电压和温度(PVT)变化的影响是广泛的。根据所获得的结果,与在非优化条件下具有相似设计的竞争对手相比,建议优化的RMAU电路对PVT变化和可噪声可容忍的标准具有稳健。所提出的优化和非优化电路用于图像处理作为真实环境评估,结果描绘了它们在各种大型可逆的应用中实施的优异能力,例如未来几代FPGA芯片和基于CNTFET的计算机。

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