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An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy

机译:一种针对视频流实时滤波的FPGA取向算法,应用于X射线荧光透视

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摘要

In this paper we propose a new algorithm for real-time filtering of video sequences corrupted by Poisson noise. The algorithm provides effective denoising (in some cases overcoming the filtering performances of state-of-the-art techniques), is ideally suited for hardware implementation, and can be implemented on a small field-programmable gate array using limited hardware resources. The paper describes the proposed algorithm, using X-ray fluoroscopy as a case study. We use IIR filters for time filtering, which largely simplifies hardware cost with respect to previous FIR filter-based implementations. A conditional reset is implemented in the IIR filter, to minimize motion blur, with the help of an adaptive thresholding approach. Spatial filtering performs a conditional mean to further reduce noise and to remove isolated noisy pixels. IIR filter hardware implementation is optimized by using a novel technique, based on Steiglitz-McBride iterative method, to calculate fixed-point filter coefficients with minimal number of nonzero elements. Implementation results using the smallest StratixIV FPGA show that the system uses only, at most, the 22% of the resources of the device, while performing real-time filtering of 1024x1024@49fps video stream. For comparison, a previous FIR filter-based implementation, on the same FPGA, in the same conditions and constraints (1024x1024@49fps), requires the 80% of the logic resources of the FPGA.
机译:在本文中,我们提出了一种新的矿泉噪声损坏的实时过滤算法。该算法提供有效的去噪(在某些情况下克服最先进的技术的过滤性能),理想地适用于硬件实现,并且可以在使用有限的硬件资源的小型现场可编程门阵列上实现。本文描述了使用X射线荧光检查的所提出的算法作为案例研究。我们使用IIR过滤器进行时间过滤,这在很大程度上简化了基于FIR滤波器的实现的硬件成本。在IIR滤波器中实现了条件复位,以便在自适应阈值处理方法的帮助下最小化运动模糊。空间滤波执行条件平均值,以进一步减少噪声并去除隔离的噪声像素。通过基于STEIGLITZ-MCBRIDE迭代方法使用新颖技术来优化IIR过滤器硬件实现,以计算具有最小数量的非零元素的定点滤波器系数。使用最小的Stratixiv FPGA的实现结果表明,系统仅使用了设备的22%,同时执行1024x1024 @ 49fps视频流的实时过滤。例如,在相同的FPGA中,在相同的条件和约束(1024x1024 @ 49fps)中,基于FIR滤波器的实现需要FPGA的80%的逻辑资源。

著录项

  • 来源
    《Circuits, systems, and signal processing》 |2019年第7期|3269-3294|共26页
  • 作者单位

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

    Univ Napoli Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Real-time video filtering; IIR filtering; IIR filter design; Poisson noise; X-ray videofluoroscopy processing; Field-programmable gate array (FPGA);

    机译:实时视频过滤;IIR滤波;IIR过滤器设计;泊松噪声;X射线videof荧光学加工;现场可编程门阵列(FPGA);

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