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High resolution FPGA pulse width modulation control of full-bridge DC–DC converters

机译:全桥DC-DC转换器的高分辨率FPGA脉冲宽度调制控制

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This study describes a field-programmable gate arrays (FPGAs) based technique, which aims to significantly improve the resolution of complementary drivers in full-bridge DC-DC converters. An algorithm for precise adjustment of both the duty cycle and the frequency of the pulse width modulator (PWM) is presented. It is experimentally verified by software simulation and FPGA hardware implementation. The results prove that the designed 12-bit digital PWM is able to provide switching frequency of 100 kHz in the range of 99.61 [99.51-99.70] kHz [mean value (95% confidence interval)] using clock frequency of just 160 MHz. In comparison, the conventional counter-based PWM gives the same output resolution at operating frequency of 410 MHz. In addition, the proposed algorithm is scalable and could be used to provide better resolution even at higher clock frequencies >400 MHz. For example, if phase-locked loop is 480 MHz then the conventional counter for 100 kHz PWM has a resolution slightly >12 bits, while the proposed algorithm could extend the resolution up to 14 bits. Due to the high reliability of the FPGA technology, the proposed PWM control is applicable in highly critical medical systems, such as electrosurgical devices.
机译:本研究描述了一种基于现场可编程的栅极阵列(FPGA)技术,其旨在显着提高全桥DC-DC转换器中互补驱动器的分辨率。提出了一种精确调整占空比和脉冲宽度调制器(PWM)的精确调整算法。它通过软件仿真和FPGA硬件实现进行了实验验证。结果证明,设计的12位数字PWM能够在99.61的范围内提供100kHz的开关频率[99.51-99.70] KHz [平均值(95%置信区间)]使用时钟频率仅为160 MHz。相比之下,传统的基于计数器的PWM为410MHz的工作频率提供相同的输出分辨率。此外,所提出的算法是可扩展的,并且即使在较高的时钟频率> 400MHz时也可用于提供更好的分辨率。例如,如果锁相环为480MHz,则传统的计数器为100kHz PWM具有略微> 12位的分辨率,而所提出的算法可以将分辨率扩展到14位。由于FPGA技术的高可靠性,所提出的PWM控制适用于高度关键的医疗系统,例如电外科设备。

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