机译:基于交错管道处理的多核时间可预测系统设计灵活的硬件方法
Silesian Tech Univ Fac Automat Control Elect & Comp Sci Ul Akad 16 PL-44100 Gliwice Poland;
Silesian Tech Univ Fac Automat Control Elect & Comp Sci Ul Akad 16 PL-44100 Gliwice Poland;
reduced instruction set computing; multi-threading; pipeline processing; field programmable gate arrays; processor scheduling; flip-flops; logic design; multiprocessing systems; interleaved pipeline processing; hardware-based approach; time-predictable electronic embedded systems; reconfigurable system architectures; ARM-like RISC solutions; hardware threads; replicated register files; deadline controlling mechanism; memory system; flexible hardware approach; multicore time-predictable systems design; reconfigurable pipelining; Virtex-7 FPGA platforms;
机译:基于带有硬件线程交错的流水线处理器的时间可预测系统
机译:群处理器系统:基于硬件过程调度程序的节能多核系统
机译:基于Aurix多核处理器的多LED动态LED系统设计
机译:基于多核处理器的非对称硬件和软件集成设计
机译:一种基于过程活动图的柔性制造系统设计方法
机译:基于Java的fMRI处理管道评估系统评估和比较基于GLM和CVA的fMRI处理管道
机译:基于多核数字信号处理器的飞行控制计算机系统的硬件设计和现场可编程门阵列