High-throughput VLSI architectures for the 1-D and 2-D discrete cosine transforms

摘要

This paper presents a linear systolic array and a 2-D systolic array for computing the 1-D N-point and 2-D N/spl times/N-point discrete cosine transforms (DCT's), respectively. The 1-D DCT array is constructed by using the Chebyshev polynomial to generate the transform kernel values recursively. The 2-D DCT array is based on the row-column decomposition but involves no matrix transposition problems, where the row and column transforms are evaluated similarly to the 1-D DCT. These architectures are highly regular, modular, and thus very suitable for VLSI implementation. Also, each of them has an efficiency of 100% and a throughput rate of one transform per N cycles. As compared to existing related systems, the proposed 1-D DCT array achieves the same time complexity with either much fewer I/O channels or a higher degree of regularity, while the proposed 2-D DCT array possesses better time complexity and regularity with an increase in chip area and I/O channels.