VLSI architectures for computing exponentiations, multiplicativeinverses, and divisions in GF(2m)

摘要

A modified parallel-in-parallel-out linear-systolic power-sumncircuit designed to perform AB2+C computations in the finitenfield GF(2m) is presented, where A, B, and C are arbitrarynelements of GF(2m). On the basis of the linear-systolicnpower-sum circuits, a VLSI architecture for exponentiation in GF(2mn) is developed. Furthermore, two modified architectures that cannbe used to compute inverses and divisions over GF(2m) arenproposed. All the architectures are constructed from m-1 linear-systolicnpower-sum circuits. It should be noted that the presented exponentiator,ninverter, and divider are the only such circuits having a throughput ofn100%. The latency of the presented pipeline exponentiator, inverter, andndivider is m(m-1) clock cycles. The cycle time (i.e., clock period) ofnthe presented architectures is only two logic gate delays plus a shortnrouting delay. For moderate values of m, say m⩽10, the circuitncomplexity of the presented circuits is realizable using presentlynavailable VLSI technology. The computation time of near two gate delaysnand 100% throughput enables the greatest computation speed in finitenfield arithmetic