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Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop

机译:用于锁相环电流匹配的增益提升电荷泵

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The charge pump (CP) circuit is a key element in a phase-locked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generates fluctuations in the voltage-controlled-oscillator input and subsequently, a large phase noise on the PLL output signals. In this brief, a new CP with good current matching characteristics is proposed. By using a simple gain-boosting circuit, good current matching characteristics can be achieved with less than 0.1% difference of the Up/Down current over the CP output voltage ranges of 0.8-2.2 V and 0.5-1.2 V on 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS processes, respectively. The proposed CP circuit is simulated and verified by HSPICE with 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS parameters
机译:电荷泵(CP)电路是锁相环(PLL)中的关键元件。其功能是将来自相位/频率检测器的Up和Down信号转换为电流。在具有分别由p沟道MOS和n沟道MOS制成的Up和Down开关的CMOS CP中,当将电荷倾倒至环路滤波器时,会发生电流不匹配的情况。 PLL中CP的这种电流失配会在压控振荡器输入中产生波动,并随后在PLL输出信号上产生较大的相位噪声。在此简介中,提出了一种具有良好电流匹配特性的新型CP。通过使用简单的增益提升电路,可以实现良好的电流匹配特性,而在0.35mm 3.3-m的CP输出电压范围0.8-2.2 V和0.5-1.2 V上,上/下电流的差异小于0.1%。 V和0.18最小的1.8V CMOS工艺。拟议的CP电路由HSPICE用0.35μm的3.3V和0.18μm的1.8V CMOS参数进行仿真和验证

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