A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing

摘要

A 10-MS/s-to-100-kS/s power-scalable fully differential comparator-based switched-capacitor (CBSC) 10-bit pipelined analog-to-digital converter (ADC) is presented. To operate over a wide range of sampling rates, an adaptive biasing technique is proposed to enhance both linearity and signal-to-noise-plusdistortion ratio (SNDR) at low sampling rates. This ADC has been fabricated in a 0.18-$muhbox{m}$ standard CMOS process. It achieves 62.3-dB spurious-free-dynamic range (SFDR) and 53.3-dB SNDR while being sampled at 10 MS/s and consuming 1.95 mW from a 1.8-V power supply, which obtains a figure of merit of 510 fJ/step. With the utilization of adaptive biasing, the SNDR increases from 53.3 to 56.4 dB at most when decreasing the sampling rate. In addition, its power consumption continuously reduces from 1.95 mW (10 MS/s) to 158.4 $muhbox{W}$ (100 kS/s).