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Residue Signal Generator Architecture With Reduced Number Of Switches For Use In A Pipeline Adc Processing Differential Signals
Residue Signal Generator Architecture With Reduced Number Of Switches For Use In A Pipeline Adc Processing Differential Signals
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机译:具有减少开关数量的残差信号发生器体系结构,用于在管道Adc中处理差分信号
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摘要
A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.
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