Realization of a Compact and High-Performance Power Divider Using Parallel RC Isolation Network

摘要

In this brief, the design methodology of high- performance lumped-distributed Wilkinson power divider with extremely small chip area is proposed. A parallel capacitor is included at the input port (port 1) to compensate the imaginary part of the input admittance for input matching. A parallel RC network is connected between the output ports (ports 2 and 3) to attain perfect input matching and isolation of the output ports in the odd- and the even-mode excitations. Dual spiral structure with transmission line length of about lambda/10 and symmetrical layout is adopted to achieve miniature area and small amplitude imbalance (AI) and phase difference (PD). At 33 GHz, the prototyped power divider achieves S-11 of -17.8 dB, S-22 and S-33 of -22.7 dB, S-32 of -34.7 dB, S-21 of -4.1 dB, and S-31 of -4.07 dB. The corresponding AI is -0.03 dB and PD is -0.08 degrees. The chip area is only 1.2 x 10(-4) lambda(2)(0), one of the smallest normalized chip area ever reported for millimeter-wave (mm-wave) power dividers. The superb results of the power divider indicate that it is suitable for power division/combination in mm-wave transceivers.