Hardware Implementation of an Improved Stochastic Computing Based Deep Neural Network Using Short Sequence Length

摘要

By introducing stochastic computing (SC), the hardware consumption of Deep Neural Network (DNN) can be reduced significantly. However, long SC sequence length is needed to maintain the accuracy, which results in extended computation time. To shorten the sequence length, we propose two high-accuracy SC computation units to improve the precision of SC-DNN, which are the rematching-based correlation-independent multiplier and the accumulator-based Rectified Linear Unit. Moreover, a length-adaptive method that uses variable lengths for different images is adopted to decrease the average sequence length. Software simulation shows that the SC design has just 0.01% accuracy loss with only the sequence length of 20 for MNIST dataset comparing to the binary system. The ASIC layout results demonstrate the area efficiency is improved by 16X comparing to the latest SC-DNN with similar accuracy loss.