A 6 $mu$ W 95 dB SNDR Inverter Based $SigmaDelta$ Modulator With Subtractive Dithering and SAR Quantizer

摘要

This brief presents a low-power Sigma Delta modulator using the subtractive dither technique. The proposed technique eliminates tones at the Sigma Delta modulator's output by injecting a dither into the quantizer. The injected dither is cancelled at the first integrator's output, which results in minimal impact on the operational transconductance amplifiers' (OTAs) output swings and enables the use of energy-efficient inverter-based OTAs. Dither is also subtracted from the digital output and has no impact on the signal-to-quantization-noise ratio. The modulator features a successive approximation register quantizer and a modified DAC which eliminates signal-dependent kick-back to the input and reference buffers. Implemented in 180-nm CMOS, the proposed modulator achieves 95.1 dB signal-to-noise-and-distortion ratio from dc to 1 kHz, and consumes only 6 mu W from a 1.2-V supply according to transient noise simulation, leading to a state-of-the-art Schreier figure-of-merit of 177.3 dB. Simulation verifies the effectiveness of subtractive dither.