...
机译:一个550- <内联 - 公式>
Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China|Univ Macau Fac Sci & Technol Macau Peoples R China;
Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China|Univ Macau Fac Sci & Technol Macau Peoples R China;
Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China|Univ Macau Dept Elect & Comp Engn Fac Sci & Technol Macau Peoples R China|Synopsys Macau Ltd Macau Peoples R China;
Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China|Univ Pavia Dept Elect I-27100 Pavia Italy;
Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China|Univ Macau Dept Elect & Comp Engn Fac Sci & Technol Macau Peoples R China;
Analog-to-digital converter (ADC); data weighting average; dynamic element matching (DEM); high linearity; incremental ADC (IADC); linear-exponential accumulation; mismatch error; multi-bit; notch; sigma delta; two phase;
机译:550-
机译:6
机译:一个6 <内联 - 公式>
机译:550µW 20kHz BW 100.8DB SNDR线性指数多位增量转换器,具有65NM CMOS的256个周期
机译:混合