机译:使用固有的非重叠时钟的0.5V 0.4至1.6GHz 8相自举环VCO实现162.2dBc / Hz FoM
Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China|Univ Macau, Fac Sci & Technol ECE, Macau, Peoples R China;
Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China;
Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China|Univ Macau, Fac Sci & Technol ECE, Macau, Peoples R China;
Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China|Univ Macau, Fac Sci & Technol ECE, Macau, Peoples R China;
Ring voltage-controlled oscillator (RVCO); low voltage; bootstrap (BT); non-overlapping clock; phase noise;
机译:5.1到7.3 mW,2.4到5 GHz的C类模式切换单端互补VCO可实现> 190 dBc / Hz FoM
机译:0.07毫米<公式>, src =“ / images / tex / 732.gif” alt =“ ^ {2}”> 公式> 2.2 mW 10 GHz电流重用B / C级实现196-dBc / Hz FoM的混合VCO
机译:5.6 nV /√Hz斩波运算放大器,采用自适应时钟增强技术,可在轨至轨输入范围内实现最大0.5μV的失调
机译:一个10 GHz 56 fsrms集成抖动和基于-247 dB FOM环形VCO的注入锁定时钟倍频器,具有65 nm CMOS的连续频率跟踪环路