A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS

摘要

Adaptive voltage frequency scaling (AVFS) techniques based on in-situ timing monitoring can mitigate the excessive timing margin caused by process, voltage and temperature (PVT) variations. However, they usually adjust the frequency by clock gating, clock half-division, or phase locked loop configuration, which cause large performance loss or need a long lock time. Thus, a compact structured adaptive clock stretching circuit is proposed here for very rapid frequency adjustment. It is very useful for AVFS systems by stretching the clock cycle with only within-a-cycle response time. The proposed architecture generates multi-phase clocks through a series of delay elements and continuously picks an appropriate phase clock to form a stretched clock. It also uses a process voltage temperature monitor to adjust the phase clock selection and makes this circuit suitable under PVT variations. Fabricated in 40-nm CMOS process, it only occupies a core area of 85*83 μm^{2. Measurements show that it can stretch the clock cycle immediately upon the stretch signal with within-a-cycle response time. It has a wide voltage range from 0.43 V to 1.1 V, with power consumptions of 38.2 μW at 0.43 V/10 MHz and 4.55 mW at 1.1 V/1.2 GHz. Plus, it can provide configurable stretch amounts for the AVFS system. Thus, it can provide a within-a-cycle, low overhead frequency adjustment solution for AVFS systems.}