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The Effect of Innerlayer Processing on Conductor Height

机译:内层处理对导体高度的影响

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摘要

Innerlayer conductor height is often well controlled and slightly thinner than the nominal expected value. The nominal thickness for half-ounce copper, for example, is 0.7 mils, but conductors in finished circuit boards oftentimes measure approximately 0.6 mils in height. The precisions of the manufacturing processes that have been developed to produce electro-deposited foil allow venders to provide foils on the low side of the thickness specification. Further, fabrication steps such as the cleaning processes that are employed to enable the photoresist to adhere to the copper, and the oxide treatments that enhance the copper-to-epoxy bond in the finished board remove some copper from the surface. Together, these factors account for the deviation from nominal copper thickness. The finished thickness of innerlayer copper traces is usually of secondary importance when compared to other parameters such as conductor width and the clearance between conductors'. Unless taken to the extreme, thinning of innerlayers will have a small impact on the capability of the conductors to carry direct current or low frequency signals. Even in higher frequency designs, the thickness of the trace has a second-order effect on controlled impedance. It is perhaps for these reasons along with time and cost factors that fabricators reprocess innerlayers when conditions permit rather than scrap them. Due to increased functionality within a smaller area and tighter impedance controls required in very high frequency applications, today's electronic circuits are more demanding then ever to fabricate. As conductors become narrower, tolerances must get tighter to achieve the desired functional requirements. OEMs and designers of printed circuit boards should be aware of the impact of innerlayer copper thickness variations on their products. To ensure signal integrity and product quality, the time has come to rethink the practice of reprocessing innerlayers.
机译:内层导体的高度通常可以很好地控制,并且比标称期望值稍薄。例如,半盎司铜的标称厚度为0.7密耳,但成品电路板上的导体的高度通常约为0.6密耳。为了生产电沉积箔而开发的制造工艺的精度允许供应商在厚度规格的低端提供箔。此外,诸如清洁工艺之类的制造步骤可用来使光致抗蚀剂粘附到铜上,而增强成品板中铜-环氧键的氧化物处理可从表面去除一些铜。这些因素共同构成了与标称铜厚度的偏差。与其他参数(例如导体宽度和导体之间的间隙)相比,内层铜走线的最终厚度通常是次要的。除非极端,否则内层的变薄将对导体承载直流或低频信号的能力产生很小的影响。即使在较高频率的设计中,走线的厚度也会对受控阻抗产生二阶影响。可能由于这些原因以及时间和成本因素,制造商在条件允许而不是报废的情况下重新加工内层。由于在较小的区域内增加了功能,并且在非常高频率的应用中需要更严格的阻抗控制,因此当今的电子电路比以往任何时候都要求更高。随着导体变窄,公差必须变小才能达到所需的功能要求。印刷电路板的OEM和设计人员应注意内层铜厚度变化对其产品的影响。为了确保信号完整性和产品质量,现在是时候重新考虑处理内层的做法了。

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