Today's high-speed FPGA designers are encountering signal integrity issues more frequently. Unfortunately, the first indication of a problem is often a prototype that works only intermittently, or only at unacceptably slow clock speeds. In production, yields may be low, or parts may have early mortality in the field. Why do so many high-speed FPGA designs suffer from signal integrity problems? The answer is simple: signal edge rates are faster than ever. The faster the edge rate, the more likely signal integrity failures will occur.
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