Signal Integrity Tips Ensure FPGA Designers Meet Critical Market Windows

摘要

Early detection, use of a virtual prototype, and an ounce of prevention may be all you need to stop SI effects in their tracks. Today, high-speed field-program-mable-gate-array (FPGA) designers encounter signal-integrity (SI) issues with increasing frequency. Unfortunately, the first indication of such a problem is often a prototype that works intermittently or has an unacceptably slow clock speed. In production, yields may be low or parts could have early mortality in the field.